From 4e131596f1defec9407b6e60d584a696beaf5d7e Mon Sep 17 00:00:00 2001
From: "David E. Box" <david.e.box@linux.intel.com>
Date: Tue, 20 Mar 2018 11:21:58 +0100
Subject: [PATCH] x86/mwait-idle: add Gemini Lake support

Gemini Lake uses the same C-states as Broxton and also uses the
IRTL MSR's to determine maximum C-state latency.

Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Acked-by: Len Brown <len.brown@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
[Linux commit 1b2e87687d3f951a66900cab6f1583d94099d2f7]
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/x86/cpu/mwait-idle.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index e357f29208..77fc3ddacc 100644
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -955,6 +955,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconstrel = {
 	ICPU(0x57, knl),
 	ICPU(0x85, knl),
 	ICPU(0x5c, bxt),
+	ICPU(0x7a, bxt),
 	ICPU(0x5f, dnv),
 	{}
 };
@@ -1100,6 +1101,7 @@ static void __init mwait_idle_state_table_update(void)
 		ivt_idle_state_table_update();
 		break;
 	case 0x5c: /* BXT */
+	case 0x7a:
 		bxt_idle_state_table_update();
 		break;
 	case 0x5e: /* SKL-H */
-- 
2.30.2